A video published by NVIDIA on their YouTube channel, and summarized for you by a combination of popular AI chatbots (Gemini, Qwen, ChatGPT, Claude). Watch it on YouTube for full credit to the authors.
Executive Summary
In his keynote at COMPUTEX 2025 on May 19th, 2025, NVIDIA CEO Jensen Huang outlined a detailed roadmap for the next phase of computing, positioning artificial intelligence as a new foundational infrastructure layer—on par with electricity and the internet. Rather than focusing on individual product SKUs, Huang presented NVIDIA as the platform provider for enterprises, industries, and nations building sovereign, scalable AI systems.
Central to this vision is the replacement of traditional data centers with “AI factories”—integrated computational systems designed to generate intelligence in the form of tokens. Huang introduced key architectural advancements including the Grace Blackwell GB300 NVL72 system, next-generation NVLink and NVSwitch fabrics, and the strategic open-sourcing of Isaac GR00T, a foundational robotics agent model.
This post dissects the three most technically significant announcements from the keynote, with a focus on implications for system architects, CTOs, and principal engineers shaping next-generation AI infrastructure.
1. The GB300 NVL72 System: Scaling AI Factories with Rack-Scale Integration
Technical Overview
The Grace Blackwell GB300 NVL72 system represents a fundamental rethinking of rack-scale AI infrastructure. Each rack contains 72 B300 GPUs and 36 Grace CPUs in a liquid-cooled configuration, delivering up to 1.4 exaflops (FP4) of AI performance. Notable improvements over the H100/H200 era include:
- ~4× increase in LLM training throughput
- Up to 30× boost in real-time inference throughput
- 192 GB of HBM3e per GPU (2.4× increase over H100)
- 5th-generation NVLink with 1.8 TB/s per GPU of bidirectional bandwidth
A 4th-generation NVSwitch fabric provides 130 TB/s of all-to-all, non-blocking bandwidth across the 72 GPUs, enabling a unified memory space at rack scale. The system operates within a 120 kW power envelope, necessitating liquid cooling and modernized power distribution infrastructure.
Architectural Implications
The GB300 NVL72 exemplifies scale-up design: high-bandwidth, tightly coupled components acting as a single compute unit. This architecture excels at training and inference tasks requiring massive memory coherence and fast interconnects.
However, scale-out—distributing computation across multiple racks—remains bottlenecked by inter-rack latency and synchronization challenges. NVIDIA appears to be standardizing the NVL72 as a modular “AI factory block,” favoring depth of integration over breadth of distribution.
The thermal and electrical demands are also transformative. 120 kW per rack mandates direct-to-chip liquid cooling, challenging legacy data center design norms.
Strategic and Competitive Context
| Feature / Vendor | NVIDIA GB300 NVL72 | AMD MI300X Platform | Google TPU v5p | Intel Gaudi 3 |
|---|---|---|---|---|
| Primary Interconnect | 5th-Gen NVLink + NVSwitch (1.8 TB/s/GPU) | Infinity Fabric + PCIe 5.0 | ICI + Optical Circuit Switch | 24× 200 GbE RoCE per accelerator |
| Scale-Up Architecture | Unified 72-GPU coherent fabric | 8-GPU coherent node | 4096-chip homogeneous pods | Ethernet-based scale-out |
| Programming Ecosystem | CUDA+, cuDNN, TensorRT | ROCm, HIP | JAX, XLA, PyTorch | SynapseAI, PyTorch, TensorFlow |
| Key Differentiator | Best-in-class scale-up performance | Open standards, cost-effective | Extreme scale-out efficiency | Ethernet-native, open integration |
Quantitative Highlights
- Performance Density: A single 120 kW GB300 NVL72 rack (1.4 EFLOPS FP4) approaches the compute capability of the 21 MW Frontier supercomputer (1.1 EFLOPS FP64), yielding over 150× higher performance-per-watt, though with different numerical precision.
- Fabric Bandwidth: At 130 TB/s, NVSwitch bandwidth within a rack exceeds peak estimated global internet backbone traffic.
- Power Efficiency: Estimated at 25–30 GFLOPS/Watt (FP8), reflecting architectural and process node advances.
2. NVLink-C2C: Opening the Fabric to a Semi-Custom Ecosystem
Technical Overview
NVIDIA announced NVLink-C2C (Chip-to-Chip), a new initiative to allow third-party silicon to participate natively in the NVLink fabric. Three key integration paths are available:
- Licensed IP Blocks: Partners embed NVLink IP in their own SoCs, ASICs, or FPGAs.
- Bridge Chiplets: Chiplet-based bridges allow legacy designs to connect without redesigning core logic.
- Unified Memory Semantics: Ensures full coherence between NVIDIA GPUs and partner accelerators or I/O devices.
This enables hybrid system architectures where NVIDIA GPUs operate alongside custom silicon—such as domain-specific accelerators, DPUs, or real-time signal processors—in a shared memory space.
Strategic Assessment
NVLink-C2C is a strategic counter to open standards like CXL and UCIe. By enabling heterogeneity within its own high-performance ecosystem, NVIDIA retains control while expanding use cases.
Success depends on:
- Partner ROI: Justifying the cost and engineering complexity of proprietary IP over CXL’s openness.
- Tooling & Validation: Supporting cross-vendor debug, trace, and profiling tools.
- Performance Guarantees: Ensuring third-party devices do not introduce latency or stall high-bandwidth links.
This move also repositions NVIDIA’s interconnect fabric as the system backplane, shifting the focus from CPUs and PCIe roots to GPUs and NVLink hubs.
Ecosystem Comparison
| Interconnect Standard | NVLink-C2C | CXL | UCIe |
|---|---|---|---|
| Use Case | GPU-accelerated chiplet/silicon cohesion | CPU-to-device memory expansion | Die-to-die physical interface for chiplets |
| Coherence Model | Full hardware coherence | CXL.cache and CXL.mem | Protocol-agnostic |
| Governance | Proprietary (NVIDIA) | Open consortium | Open consortium |
| Strategic Goal | GPU-centric heterogeneous integration | Broad heterogeneity and ecosystem access | Chiplet disaggregation across vendors |
Confirmed partners: MediaTek, Broadcom, Cadence, Synopsys.
3. Isaac GR00T and the Rise of Physical AI
Technical Overview
Huang identified a strategic shift toward embodied AI—autonomous agents that operate in the physical world. NVIDIA’s stack includes:
- Isaac GR00T (Generalist Robot 00 Technology): A robotics foundation model trained on multimodal demonstrations—text, video, and simulation. Designed to be robot-agnostic.
- Isaac Lab & Omniverse Sim: A highly parallelized simulation environment for training and validating policies via reinforcement learning and sim-to-real pipelines.
- Generative Simulation: AI-generated synthetic data and environments, reducing dependence on real-world data collection.
Together, these components define a full-stack, simulation-first approach to training robotics agents.
Challenges and Opportunities
While simulation fidelity continues to improve, the sim-to-real gap remains the key barrier. Discrepancies in dynamics, perception noise, and actuator behavior can derail even well-trained policies.
Other critical considerations:
- Safety and Alignment: Embodied AI introduces physical risk; rigorous validation and fail-safe mechanisms are mandatory.
- Fleet Orchestration: Deploying, updating, and monitoring robots in real-world environments requires industrial-grade orchestration platforms.
- Edge Compute Requirements: Real-time control necessitates high-performance, low-latency hardware—hence NVIDIA’s positioning of Jetson Thor as the robotics edge brain.
Competitive Landscape
| Company / Platform | NVIDIA Isaac | Boston Dynamics | Tesla Optimus | Open Source (ROS/ROS 2) |
|---|---|---|---|---|
| AI Approach | Foundation model + sim-to-real | Classical control + RL | End-to-end neural (vision-to-actuation) | Modular, limited AI integration |
| Simulation | Omniverse + Isaac Lab | Proprietary | Proprietary | Gazebo, Webots |
| Business Model | Horizontal platform + silicon | Vertically integrated hardware | In-house for vehicle automation | Community-led, vendor-neutral |
Strategic Implications for Technology Leaders
1. Re-Architect the Data Center for AI Factory Workloads
- Plan for 120 kW/rack deployments, with liquid cooling and revamped power infrastructure.
- Network performance is system performance: fabrics like NVSwitch must be part of core architecture.
- Talent pipeline must now blend HPC, MLOps, thermal, and hardware engineering.
2. Engage in Heterogeneous Compute—But Know the Tradeoffs
- NVLink-C2C offers deep integration but comes at the cost of proprietary lock-in.
- CXL and UCIe remain credible alternatives—balance performance against openness and cost.
3. Prepare for Digital-Physical AI Convergence
- Orchestration frameworks must span cloud, edge, and robotic endpoints.
- Edge inferencing and data pipelines need tight integration with simulation and training platforms.
- Robotics will demand security, safety, and compliance architectures akin to automotive-grade systems.
Conclusion
Jensen Huang’s COMPUTEX 2025 keynote declared the end of general-purpose computing as the default paradigm. In its place: AI-specific infrastructure spanning silicon, system fabrics, and simulation environments. NVIDIA is building a full-stack platform to dominate this new era—from rack-scale AI factories to embodied agents operating in the physical world.
But this vision hinges on a proprietary ecosystem. The counterweights—open standards, cost-conscious buyers, and potential regulatory scrutiny—will define whether NVIDIA’s walled garden becomes the new industry blueprint, or a high-performance outlier amid a more modular and open computing future.
For CTOs, architects, and engineering leaders: the choice is not just technical—it is strategic. Infrastructure decisions made today will determine whether you’re building on granite or sand in the coming decade of generative and physical AI.